8P391208NLGI

Features

• Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS reference clocks

• Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz (up to 1GHz when configured into HCSL output mode at 3.3V)

• Select which of the two input clocks is to be used as the reference clock for which bank via pin selection

• Generates 8 differential outputs

• Differential outputs selectable as LVPECL, LVDS, CML or HCSL

• CML mode supports two different voltage swings

• Differential outputs support frequencies from 1PPS to 700MHz (up to 1GHz when configured into HCSL output mode at 3.3V)

• Outputs arranged in 2 banks of 4 outputs each

• Each bank supports a separate power supply of 3.3V, 2.5V or 1.8V

• Controlled by 3-level input pins

• Input mux selection control pin

• Control inputs are 3.3V-tolerant for all core voltages

• Output noise floor of -153dBc/Hz @ 156.25MHz

• Core voltage supply of 3.3V, 2.5V or 1.8V

• -40°C to +85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

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