CY7C1360C-166AXC

The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells.

The Burst Control inputs (ADSC, ADSP, and ADV) in the CY7C1360C/CY7C1362C SRAM are used for controlling the address advancement through the burst sequence. When ADSP or ADSC is asserted LOW, addresses presented to the device are captured in the address registers. The ADV input controls the address advancement through the burst sequence by automatically incrementing the address for the rest of the burst access. These inputs play a crucial role in initiating and controlling the burst accesses in the SRAM.

The available speed grades for the CY7C1360C/CY7C1362C SRAM are 250, 200, and 166 MHz.