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N65LVDS94

LVDS Interface IC LVDS Serder Receiver

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N65LVDS94

LVDS Interface IC LVDS Serder Receiver

Gli ordini superiori a $ 200 hanno diritto a un regalo in stile cinese in edizione limitata.

Gli ordini superiori a $ 200 hanno diritto a un regalo in stile cinese in edizione limitata.

Gli ordini superiori a $ 1000 beneficiano di un'esenzione dalle spese di spedizione di $ 30.

Gli ordini superiori a $ 5000 beneficiano dell'esenzione dalle spese di spedizione e di transazione.

Queste offerte sono applicabili sia ai clienti nuovi che a quelli esistenti e sono valide dal 1 gennaio 2024 al 31 dicembre 2024.

  • Produttore:

    TI

  • Scheda dati:
  • Pacchetto/custodia:

    TSSOP-56

  • categoria di prodotto:

    Circuiti integrati RF

  • DataCodice:

Invia la tua richiesta di preventivo adesso e prevediamo di fornirti un preventivo entro marzo 30, 2024. Effettua ora il tuo ordine e prevediamo di completare la transazione entro aprile 04, 2024. Ps: L'orario è secondo GMT+8:00.

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Azione:1 PCS

Il nostro impegno è fornire preventivi tempestivi entro 12 ore. Per ulteriore assistenza, contattaci all'indirizzo sales@censtry.com.

N65LVDS94 Dettagli del prodotto

FEATURES

• 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput

• Suited for Point-to-Point Subsystem Communication With Very Low EMI

• 4 Data Channels and Clock Low-Voltage Differential Channels in and 28 Data and Clock Out Low-Voltage TTL Channels Out

• Operates From a Single 3.3-V Supply and 250 mW (Typ)

• 5-V Tolerant SHTDN Input

• Rising Clock Edge Triggered Outputs

• Bus Pins Tolerate 4-kV HBM ESD

• Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch

• Consumes <1 mW When Disabled

• Wide Phase-Lock Input Frequency Range 20 MHz to 68 MHz

• No External Components Required for PLL

• Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard

• Industrial Temperature Qualified TA = -40°C to 85°C

• Replacement for the DS90CR286



GENERAL DESCRIPTION

The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.


When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).


The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.


The SN65LVDS94 is characterized for operation over ambient air temperatures of -4 °C to 85°C.


Request a quote N65LVDS94 at censtry.com. All items are new and original with 365 days warranty! The excellent quality and guaranteed services of N65LVDS94 in stock for sale, check stock quantity and pricing, view product specifications, and order contact us:sales@censtry.com.
The price and lead time for N65LVDS94 depending on the quantity required, please send your request to us, our sales team will provide you price and delivery within 24 hours, we sincerely look forward to cooperating with you.

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