The currently designed FPGA board uses the FPGA model XC7Z100-FFG900. Recently, there was a problem during joint debugging with the customer. The FPGA has several GPIOs that are connected to the customer board through the connector, and the customer's board corresponds to the pin Long-term in the 3.3V high level state. After connecting to the GPIO of our single board, our FPGA cannot be loaded normally. The GPIO pins are directly connected from the FPGA to the inter-board connector, and the connector is disconnected to return to normal. After testing, it is found that due to the high level of the opposite end of the GPIO link, the voltage of our GPIO corresponding to BANK's VCCO33 is pulled up to about 2.1V. In theory, the INPUT pin of the FPGA is in a high impedance state at this time. I don't know why this happens. In this scenario, I found a few boards and tried them later, and this problem still exists.
Please refer to the schematic diagram. In fact, the GPIO is directly pulled from the FPGA to the inter-board connector, and there is no other link.
Maxwell postato su September 21, 2020
You can try adding a triode or MOS tube to isolate it, don't connect it directly.
Vanessa postato su September 21, 2020
This phenomenon should be due to power backflow, which has caused the FPGA end to remain in an unstable state. There is also a voltage inside the FPGA when the power is off, and the chip is not reset correctly. You can put a larger resistor on the signal line to try it, or FPGA Add a reset chip
Angelina postato su September 21, 2020
Is IO unidirectional or bidirectional? If it is one-way, isolate the price of a triode. If it is two-way, add a chip. Use the power supply on the FPGA side to control the enable, so that the enable can be turned on after the FPGA is powered on, which can solve the power backflow.
